make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libcompiler_rt'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       mdio.o
 AR       libbase.a
 AR       libbase-nofloat.a
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libbase'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libnet'
 CC       microudp.o
 AR       libnet.a
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libnet'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/bios'
 CC       isr.o
 CC       sdram.o
 CC       main.o
 CC       boot.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/bios'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libcompiler_rt'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       mdio.o
 AR       libbase.a
 AR       libbase-nofloat.a
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libbase'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libnet'
 CC       microudp.o
 AR       libnet.a
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/libnet'
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/bios'
 CC       isr.o
 CC       sdram.o
 CC       main.o
 CC       boot.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/software/bios'
For now I do not know if memory map looks different!
SC: Check how to get cpu_reset_addr properly!!!!!!!!
HEY
/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard
/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard
make: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware'
mkdir -p /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir
make -C /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules
make[1]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules'
make -C ethernet
make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/ethernet'
gcc -c -Wall -O3 -ggdb -fPIC -Werror -Itapcfg/src/include -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.o ethernet.c
gcc -Wall -O3 -ggdb -fPIC -Werror -Itapcfg/src/include -c -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/tapcfg.o tapcfg/src/lib/tapcfg.c
gcc -Wall -O3 -ggdb -fPIC -Werror -Itapcfg/src/include -c -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/taplog.o tapcfg/src/lib/taplog.c
gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/ethernet.o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/tapcfg.o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/taplog.o
make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/ethernet'
make -C serial2console
make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2console'
gcc -c -Wall -O3 -ggdb -fPIC -Werror -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.o serial2console.c
gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.o
rm /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2console.o
make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2console'
make -C serial2tcp
make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2tcp'
gcc -c -Wall -O3 -ggdb -fPIC -Werror -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.o serial2tcp.c
gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.o
rm /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/serial2tcp.o
make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/serial2tcp'
make -C clocker
make[2]: Entering directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/clocker'
gcc -c -Wall -O3 -ggdb -fPIC -Werror -I../.. -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.o clocker.c
gcc -levent -shared -fPIC -Wl,-soname,/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.so -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.so /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.o
rm /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/clocker.o
make[2]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules/clocker'
make[1]: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules'
gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/modules.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/modules.c
gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/pads.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/pads.c
gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/sim.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/sim.c
/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/sim.c: In function 'main':
/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/sim.c:227:3: warning: implicit declaration of function 'litex_sim_init_cmdargs' [-Wimplicit-function-declaration]
   litex_sim_init_cmdargs(argc, argv);
   ^
gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/libdylib.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/libdylib.c
gcc -c -Wall -O3 -ggdb  -o /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/obj_dir/parse.o /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/parse.c
verilator -Wno-fatal -O3 --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce1_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_transducer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_mock_fe.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce8_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_lce.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce4_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/mock_tlb.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_fsm_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_pipe_fp.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_aviary_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce4_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_alu.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_nonsynth_tracer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_id_to_cord.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce8_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_tile_node.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce4_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_csr.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce1_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce4_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_btb.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_pc.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_lce.v --cc /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/dut.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce16_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce16_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_fifo_1r1w_rolly.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_decompress.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_nonsynth_lce_tracer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/channel_test2.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_mem_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_tile.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_to_manycore_link_rx.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_stat_info.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce8_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_ptw.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_addr_map.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_checker_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_storage_sync.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce8_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce2_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_to_manycore_link.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce2_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce32_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/test_bp.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_delay_model.v --cc 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/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce2_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_trace_node_master.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_mock_ptw.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_fsm.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce1_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_detector.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_nonsynth_tracer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_to_wormhole_link_client.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce4_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_director.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_mem_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_csr_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_rv64_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg_cached.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_wormhole_packet_encode_lce_cmd.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg_uncached.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce1_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_mem_if.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_dir_tag_checker.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/channel_test3.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce8_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_core.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_lce_cmd.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_instr_scan.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_fe_be_if.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_nonsynth_perf.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce1_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce1_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce16_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_gad.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_lce_req.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_me_if.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce4_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_rv64_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/mock_be_tb.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce16_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_noc_links.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_icache.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_defines.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_lce_pkt.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce16_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_pipe_int.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_wormhole_router.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_wormhole_packet_encode_lce_resp.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce4_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce32_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_rolly_lce_me.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce1_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce1_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_regfile.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_ctl_defines.vh  --top-module dut --exe \
	-DPRINTF_COND=0 \
	dut_init.cpp /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \
	--top-module dut \
	 \
	-CFLAGS "-Wall -O3 -ggdb  -I/home/scanakci/Research_sado/litex/litex/litex/build/sim/core" \
	-LDFLAGS "-lpthread -ljson-c -lm -lstdc++ -ldl -levent" \
	--trace \
	 \
	--unroll-count 256 \
	-I/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard  \
	-Wno-BLKANDNBLK \
	-Wno-WIDTH
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:5: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER
 import bp_common_pkg::*;
        ^~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:14: Define or directive not defined: '`declare_bp_proc_params'
   `declare_bp_proc_params(cfg_p)
   ^~~~~~~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:15: Define or directive not defined: '`declare_bp_me_if_widths'
   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
   ^~~~~~~~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:17: Define or directive not defined: '`bsg_ready_and_link_sif_width'
   , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p)
                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:18: syntax error, unexpected ')', expecting ';'
   )
   ^
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:43: Define or directive not defined: '`declare_bp_me_if'
`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p);
^~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:49: syntax error, unexpected IDENTIFIER
bp_cce_mem_msg_s mem_resp_lo;
^~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:52: Define or directive not defined: '`BSG_SAFE_CLOG2'
localparam lg_num_core_lp = `BSG_SAFE_CLOG2(num_core_p);
                            ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:61: syntax error, unexpected always_comb
always_comb
^~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:95: syntax error, unexpected IDENTIFIER
bsg_decode_with_v
^~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:124: syntax error, unexpected assign
assign mtime_n    = mtime_w_v_li 
^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:149: syntax error, unexpected IDENTIFIER
bsg_decode_with_v
^~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:153: Define or directive not defined: '`BSG_SAFE_CLOG2'
   ,.i(cfg_core_li[0+:`BSG_SAFE_CLOG2(num_core_p)])
                      ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:161: syntax error, unexpected IDENTIFIER
    bsg_dff_reset_en
    ^~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:175: syntax error, unexpected IDENTIFIER
    bsg_dff_reset_en
    ^~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:189: syntax error, unexpected IDENTIFIER
    bsg_dff_reset_en
    ^~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:204: syntax error, unexpected assign
    assign cfg_w_v_o[i]  = cfg_w_v_li | cfg_broadcast_li;
    ^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:210: syntax error, unexpected IDENTIFIER
bsg_mux_one_hot
^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:221: syntax error, unexpected IDENTIFIER
bsg_mux_one_hot
^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:232: syntax error, unexpected IDENTIFIER
bsg_mux_one_hot
^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v:250: syntax error, unexpected assign
assign mem_resp_lo =
^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:15: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER
  import bp_common_pkg::*;
         ^~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:20: Define or directive not defined: '`declare_bp_proc_params'
    `declare_bp_proc_params(cfg_p)
    ^~~~~~~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:20: syntax error, unexpected '(', expecting ';'
    `declare_bp_proc_params(cfg_p)
                            ^~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:24: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam lg_num_lce_lp             = `BSG_SAFE_CLOG2(num_lce_p)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:24: Define or directive not defined: '`BSG_SAFE_CLOG2'
    , localparam lg_num_lce_lp             = `BSG_SAFE_CLOG2(num_lce_p)
                                             ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:25: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam lg_num_cce_lp             = `BSG_SAFE_CLOG2(num_cce_p)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:25: Define or directive not defined: '`BSG_SAFE_CLOG2'
    , localparam lg_num_cce_lp             = `BSG_SAFE_CLOG2(num_cce_p)
                                             ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:26: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:26: Define or directive not defined: '`BSG_SAFE_CLOG2'
    , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp)
                                             ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:27: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam lg_lce_assoc_lp           = `BSG_SAFE_CLOG2(lce_assoc_p)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:27: Define or directive not defined: '`BSG_SAFE_CLOG2'
    , localparam lg_lce_assoc_lp           = `BSG_SAFE_CLOG2(lce_assoc_p)
                                             ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:28: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam lg_lce_sets_lp            = `BSG_SAFE_CLOG2(lce_sets_p)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:28: Define or directive not defined: '`BSG_SAFE_CLOG2'
    , localparam lg_lce_sets_lp            = `BSG_SAFE_CLOG2(lce_sets_p)
                                             ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:29: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam num_way_groups_lp         = (lce_sets_p/num_cce_p)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:30: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam lg_num_way_groups_lp      = `BSG_SAFE_CLOG2(num_way_groups_lp)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:30: Define or directive not defined: '`BSG_SAFE_CLOG2'
    , localparam lg_num_way_groups_lp      = `BSG_SAFE_CLOG2(num_way_groups_lp)
                                             ^~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:31: syntax error, unexpected localparam, expecting IDENTIFIER
    , localparam mshr_width_lp = `bp_cce_mshr_width(num_lce_p, lce_assoc_p, paddr_width_p)
      ^~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:31: Define or directive not defined: '`bp_cce_mshr_width'
    , localparam mshr_width_lp = `bp_cce_mshr_width(num_lce_p, lce_assoc_p, paddr_width_p)
                                 ^~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:31: syntax error, unexpected ','
    , localparam mshr_width_lp = `bp_cce_mshr_width(num_lce_p, lce_assoc_p, paddr_width_p)
                                                             ^
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:34: Define or directive not defined: '`declare_bp_lce_cce_if_widths'
    `declare_bp_lce_cce_if_widths(num_cce_p, num_lce_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:35: Define or directive not defined: '`declare_bp_me_if_widths'
    `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
    ^~~~~~~~~~~~~~~~~~~~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:50: syntax error, unexpected input, expecting IDENTIFIER or do or final
   , input [lce_cce_resp_width_lp-1:0]                 lce_resp_i
     ^~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:54: syntax error, unexpected output, expecting IDENTIFIER or do or final
   , output logic [lce_cmd_width_lp-1:0]               lce_cmd_o
     ^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:55: syntax error, unexpected output, expecting IDENTIFIER or do or final
   , output logic                                      lce_cmd_v_o
     ^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:56: syntax error, unexpected input, expecting IDENTIFIER or do or final
   , input                                             lce_cmd_ready_i
     ^~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:65: syntax error, unexpected input, expecting IDENTIFIER or do or final
   , input [cce_mem_msg_width_lp-1:0]                  mem_cmd_i
     ^~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:69: syntax error, unexpected output, expecting IDENTIFIER or do or final
   , output logic [cce_mem_msg_width_lp-1:0]           mem_cmd_o
     ^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:70: syntax error, unexpected output, expecting IDENTIFIER or do or final
   , output logic                                      mem_cmd_v_o
     ^~~~~~
%Error: /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v:71: syntax error, unexpected input, expecting IDENTIFIER or do or final
   , input                                             mem_cmd_ready_i
     ^~~~~
%Error: Exiting due to too many errors encountered; --error-limit=50
%Error: Command Failed /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/external/bin/verilator_bin -Wno-fatal -O3 --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce1_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mmio_enclave.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_msg.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_transducer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_mock_fe.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce8_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_lce.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce4_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/mock_tlb.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_fsm_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_pipe_fp.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_aviary_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce4_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_alu.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_nonsynth_tracer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_id_to_cord.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce8_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_tile_node.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce4_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_csr.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce1_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce4_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_btb.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_pc.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_lce.v --cc /home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware/dut.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce16_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce16_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_fifo_1r1w_rolly.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_decompress.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_nonsynth_lce_tracer.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/channel_test2.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_mem_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_tile.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_to_manycore_link_rx.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_stat_info.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce8_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_ptw.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_addr_map.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_checker_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_storage_sync.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce8_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce2_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_to_manycore_link.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce2_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce32_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/test_bp.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_delay_model.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce16_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_to_wormhole_link_master.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_lce_id_to_cord.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce8_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_top.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_nonsynth_if_verif.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce4_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_dir.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce8_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_mmio_cfg_loader.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_mem_complex.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce4_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_tag_info.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce4_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce16_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_core_complex.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce2_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_pc_gen.v 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/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_cce_mem_if.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_dir_tag_checker.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/channel_test3.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce8_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_core.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_lce_cmd.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_instr_scan.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_fe_be_if.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_nonsynth_perf.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce1_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce16_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce1_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce16_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_gad.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_lce_req.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_me_if.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce4_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_rv64_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/mock_be_tb.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce16_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_noc_links.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_icache.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_fe_defines.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_defines.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce8_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_common_pkg.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_dcache_lce_pkt.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce16_wg2_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_pipe_int.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bsg_wormhole_router.vh --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce32_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_me_wormhole_packet_encode_lce_resp.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce4_wg32_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_msi_lce2_wg8_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce32_wg4_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_rolly_lce_me.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_ei_lce1_wg16_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_cce_inst_rom_mesi_lce1_wg64_assoc8.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_regfile.v --cc /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard/bp_be_ctl_defines.vh --top-module dut --exe -DPRINTF_COND\=0 dut_init.cpp /home/scanakci/Research_sado/litex/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o --top-module dut -CFLAGS -Wall\ -O3\ -ggdb\ \ -I/home/scanakci/Research_sado/litex/litex/litex/build/sim/core -LDFLAGS -lpthread\ -ljson-c\ -lm\ -lstdc\+\+\ -ldl\ -levent --trace --unroll-count 256 -I/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/verilog/standard -Wno-BLKANDNBLK -Wno-WIDTH
/home/scanakci/Research_sado/litex/litex/litex/build/sim/core/Makefile:29: recipe for target 'sim' failed
make: *** [sim] Error 10
make: Leaving directory '/home/scanakci/Research_sado/litex/litex/litex/tools/simout2/gateware'